SpacemiT V100: A 46-Core Server-Class RISC-V Chip

SpacemiT announced the V100, which it calls the first chip fully compliant with the RISC-V server specification.

• 46 cores in a hybrid design: 6 XiangShan Kunminghu V2R2 cores and 40 SpacemiT X100 cores, at 2.2-2.4 GHz.
• Up to two sockets, so 92 cores per server.
• 12nm, 120W TDP, eight-channel DDR5-4800 and 52 lanes of PCIe 5.0.
• UEFI, ACPI and SMBIOS support, which is what makes a server boot normal distros without hacks.

It won’t touch current Xeon, EPYC or Arm server chips on raw performance, as Phoronix notes. But standards compliance is the boring prerequisite RISC-V servers need.

My take

RISC-V keeps creeping up the stack. Pair this with Ubuntu’s RISC-V desktop images and the open ISA keeps getting more real.

References & Further Reading

• SpacemiT V100 (Phoronix)